1. Field of the Invention
The present invention relates to a process for forming of differential spacers in electronic devices integrated on a semiconductor substrate.
The invention particularly, but not exclusively, relates to a process for forming differential spacers in floating gate non-volatile memory devices and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, non-volatile memory electronic devices, for example of the Flash type, integrated on semiconductor substrate comprise a matrix of non-volatile memory cells organized in rows, called word lines, and columns, called bit lines.
Each single non-volatile memory cell comprises a MOS transistor wherein the gate electrode, arranged above the channel region, is floating, i.e., it shows high impedance in DC towards all the other terminals of the same cell and of the circuit wherein the cell is inserted.
The cell also comprises a second electrode, called the control gate, which is capacitively coupled to the floating gate electrode through an intermediate dielectric layer, so called interpoly. This second electrode is driven through suitable control voltages. The other electrodes of the transistor are the usual drain, source terminals.
The cells belonging to a same word line share the electric line which drives the respective control gates, while the cells belonging to a same bit line share the drain terminals.
Conventionally, memory electronic devices also comprise control circuitry associated with the matrix of memory cells. The control circuitry comprises conventional high voltage (HV) MOS transistors, each one having a source region and a drain region separated by a channel region. A gate electrode is then formed on the channel region and insulated therefrom by a gate oxide layer.
Moreover, spacers are present on the side walls of the gate electrodes.
However, in new generation memory devices the circuitry also comprises low voltage (LV) transistors with high performances in particular for embedded applications and for carrying out, at high speed, the complex management algorithms of the memory devices themselves. The process steps for forming these advanced technology LV transistors, especially those pertaining to the formation of the junction implants (source and drain regions) and of the spacers are particularly complex. In particular, the integration of the high performance LV transistors with the HV transistors handling the high voltages for writing to the memory cells is further complex, with the need of introducing differential spacers and junction implants.
The known process solutions currently in use provide that the circuitry spacers are formed also in the memory matrix, possibly with differential processes, and that the circuitry spacers are formed by nitride films and rather thick oxide layers.
Although advantageous under several aspects, this solution shows several drawbacks.
In fact, these process steps are not necessary for the formation of non-volatile memory cells, for example, with NOR or NAND architecture, whose source and drain regions are usually defined in a self-aligned way to the gate electrodes and for which the spacers are non-necessary elements which can become a heavy limitation for the scalability of the cell, in particular for the salicidation of the drain regions, for filling with premetal dielectric layers, for the integration of the drain contact and for the sustainability of the reading disturbances.